\doxysection{USART\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_u_s_a_r_t___type_def}{}\label{struct_u_s_a_r_t___type_def}\index{USART\_TypeDef@{USART\_TypeDef}}


Universal Synchronous Asynchronous Receiver Transmitter.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a6d7dcd3972a162627bc3470cbf992ec4}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_aa7ede2de6204c3fc4bd9fb328801c99a}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_af2991da9a4e1539530cd6b7b327199cc}{CR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a6ef06ba9d8dc2dc2a0855766369fa7c9}{BRR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_ae23acff49b4ff96fd29093e80fc7d72e}{GTPR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a5732c379e1ce532552e80392db4eabf8}{RTOR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_add7a9e13a3281f6bea133b3693ce68f8}{RQR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a79ce09e9fbedb2d169b3a584ed003b02}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_ab6d6dd2af5463e9e3df458557e09f6cf}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a8d538b7390289142b70428c5b0af0a18}{RDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_a315ab2fb3869668e7c5c12e8204efe10}{TDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_u_s_a_r_t___type_def_abe251663891063ada5a08d269c1d71a2}{PRESC}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Universal Synchronous Asynchronous Receiver Transmitter. 

\label{doc-variable-members}
\Hypertarget{struct_u_s_a_r_t___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_u_s_a_r_t___type_def_a6ef06ba9d8dc2dc2a0855766369fa7c9}\index{USART\_TypeDef@{USART\_TypeDef}!BRR@{BRR}}
\index{BRR@{BRR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BRR}{BRR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a6ef06ba9d8dc2dc2a0855766369fa7c9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+BRR}

USART Baud rate register, Address offset\+: 0x0C \Hypertarget{struct_u_s_a_r_t___type_def_a6d7dcd3972a162627bc3470cbf992ec4}\index{USART\_TypeDef@{USART\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a6d7dcd3972a162627bc3470cbf992ec4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+CR1}

USART Control register 1, Address offset\+: 0x00 \Hypertarget{struct_u_s_a_r_t___type_def_aa7ede2de6204c3fc4bd9fb328801c99a}\index{USART\_TypeDef@{USART\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_aa7ede2de6204c3fc4bd9fb328801c99a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+CR2}

USART Control register 2, Address offset\+: 0x04 \Hypertarget{struct_u_s_a_r_t___type_def_af2991da9a4e1539530cd6b7b327199cc}\index{USART\_TypeDef@{USART\_TypeDef}!CR3@{CR3}}
\index{CR3@{CR3}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR3}{CR3}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_af2991da9a4e1539530cd6b7b327199cc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+CR3}

USART Control register 3, Address offset\+: 0x08 \Hypertarget{struct_u_s_a_r_t___type_def_ae23acff49b4ff96fd29093e80fc7d72e}\index{USART\_TypeDef@{USART\_TypeDef}!GTPR@{GTPR}}
\index{GTPR@{GTPR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{GTPR}{GTPR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_ae23acff49b4ff96fd29093e80fc7d72e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+GTPR}

USART Guard time and prescaler register, Address offset\+: 0x10 \Hypertarget{struct_u_s_a_r_t___type_def_ab6d6dd2af5463e9e3df458557e09f6cf}\index{USART\_TypeDef@{USART\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_ab6d6dd2af5463e9e3df458557e09f6cf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+ICR}

USART Interrupt flag Clear register, Address offset\+: 0x20 \Hypertarget{struct_u_s_a_r_t___type_def_a79ce09e9fbedb2d169b3a584ed003b02}\index{USART\_TypeDef@{USART\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a79ce09e9fbedb2d169b3a584ed003b02} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+ISR}

USART Interrupt and status register, Address offset\+: 0x1C \Hypertarget{struct_u_s_a_r_t___type_def_abe251663891063ada5a08d269c1d71a2}\index{USART\_TypeDef@{USART\_TypeDef}!PRESC@{PRESC}}
\index{PRESC@{PRESC}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PRESC}{PRESC}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_abe251663891063ada5a08d269c1d71a2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+PRESC}

USART clock Prescaler register, Address offset\+: 0x2C \Hypertarget{struct_u_s_a_r_t___type_def_a8d538b7390289142b70428c5b0af0a18}\index{USART\_TypeDef@{USART\_TypeDef}!RDR@{RDR}}
\index{RDR@{RDR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RDR}{RDR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a8d538b7390289142b70428c5b0af0a18} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+RDR}

USART Receive Data register, Address offset\+: 0x24 \Hypertarget{struct_u_s_a_r_t___type_def_add7a9e13a3281f6bea133b3693ce68f8}\index{USART\_TypeDef@{USART\_TypeDef}!RQR@{RQR}}
\index{RQR@{RQR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RQR}{RQR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_add7a9e13a3281f6bea133b3693ce68f8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+RQR}

USART Request register, Address offset\+: 0x18 \Hypertarget{struct_u_s_a_r_t___type_def_a5732c379e1ce532552e80392db4eabf8}\index{USART\_TypeDef@{USART\_TypeDef}!RTOR@{RTOR}}
\index{RTOR@{RTOR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RTOR}{RTOR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a5732c379e1ce532552e80392db4eabf8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+RTOR}

USART Receiver Time Out register, Address offset\+: 0x14 \Hypertarget{struct_u_s_a_r_t___type_def_a315ab2fb3869668e7c5c12e8204efe10}\index{USART\_TypeDef@{USART\_TypeDef}!TDR@{TDR}}
\index{TDR@{TDR}!USART\_TypeDef@{USART\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TDR}{TDR}}
{\footnotesize\ttfamily \label{struct_u_s_a_r_t___type_def_a315ab2fb3869668e7c5c12e8204efe10} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t USART\+\_\+\+Type\+Def\+::\+TDR}

USART Transmit Data register, Address offset\+: 0x28 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
